1. Field of the Invention
The invention relates in general to a read-only memory, particularly to a read-only memory with a reduced loading value of bit lines.
2. Description of the Related Art
As the information industry matures, the demands for read-only memory increases. One of the main areas of research in the information industry is on how to improve accuracy while retrieving data contained in read-only memory.
FIG. 1 illustrates the equivalent circuit diagram of a traditional read-only memory. The read-only memory 100 usually includes multiple memory banks, such as the nth memory bank, Bank (n), and the (n+1)th memory bank, Bank (n+1). Each memory bank is composed of multiple memory cells B to form a memory array. Each memory cell B is for storing 1-bit binary data. Each memory cell B is implemented by a transistor. During the manufacturing process, each memory cell B is made to have different threshold voltage Vt according to the data to be stored. If the memory cell B is for storing data of 0, it has a high threshold voltage; if the memory cell B is for storing data of 1, it has a low threshold voltage. Selecting switches are controlled by selecting lines SL1xcx9cSL4. For example, the selecting switch M24(n) enables a main bit line BL(n) to be electrically connected to some of the sub-bit lines, such as sub-bit line SB4(n). The selecting switches are also implemented by transistors. In FIG. 1, a transistor marked with the symbol X represents a transistor with high threshold voltage; a transistor without an X is a transistor with low threshold voltage.
When reading memory cell B, which is in the nth memory bank Bank(n) and is controlled by a word line WL0, the operation of the circuit is described as follows: First, the main bit line BL(n) is connected to a sense amplifier SA and the main bit line GL(n+1) is connected to the ground end GND. At the same time, the selecting lines SL2 and SL4 are enabled and the word line WL0 corresponding to the memory cell B is enabled in order to turn on the memory cell B. Therefore, the current output from the sense amplifier SA flows through the main bit line BL(n), the selecting switch M24(n), the memory cell B, the selecting switch M42(n+1), and the main bit line GL(n+1), and then reaches the ground end GND, as the current path P shows. The content value of the memory cell B can be read by the sense amplifier SA sensing the value of the output current. If memory cell B has low threshold voltage, which represents the data of logic 1, the sense amplifier SA will sense a large current.
When reading the memory cell B, the current only flows along the current path P. And the equivalent resistance value of the current path P is the sum of the equivalent resistance values of the selecting switches M24(n) and M42(n+1), and the equivalent resistance value of the partial sub-bit lines SB4(n) and SB1(n+1). As the layout technology progresses, the width of bit lines decreases. Due to the inversely proportional relationship between the value of a resistance and the width of a bit line, the bit line resistance value increases. When inputting the same voltage, the output current decreases as the resistance becomes larger. Therefore, the decreased current of the current path P lowers the sensing accuracy of the sense amplifier. Thus, it is necessary to find a solution to reduce the loading value and then increase the current, in order to avoid errors by the sense amplifier SA.
It is therefore an object of this invention to provide a read-only memory with a lower loading value. By adding multiple rows of auxiliary switches, multiple current paths can be formed to reduce the loading value when reading a specific memory cell. Therefore, the current can be amplified, and the error by the sense amplifier can be decreased.
It is another object of this invention to provide a read-only memory, which includes multiple word lines parallel to each other. The read-only memory includes K memory banks. One of the K memory banks is an nth memory bank. The nth memory bank includes s a first main bit line BL(n), multiple first selecting switches, multiple second selecting switches, a first sub-bit line SB1(n), a second sub-bit line SB2(n), a third sub-bit line SB3(n), a fourth sub-bit line SB4(n), multiple first auxiliary switches, multiple second auxiliary switches, and multiple memory cells. Multiple first and second select switches are controlled by the first and the second select lines respectively. When these first selecting switches are turned on, the first bit line BL(n) is electrically connected to the second sub-bit line SB2(n) and the third sub-bit line SB3(n). When the second selecting switches are turned on, the first main bit line BL(n) is electrically connected to the third sub-bit line SB3(n) and the fourth sub-bit line SB4(n). A first auxiliary line SL1 controls the first auxiliary switches, and a second auxiliary line SL2 controls the second auxiliary switches. Some of the first and the second auxiliary switches have low threshold voltage, and word lines control multiple memory cells. Each memory cell is connected between two sub-bit lines. When a current flows through one of the memory cells, the current at least flow through one of the first or second auxiliary switches that are turned on.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.